<html><body><samp><pre>
<!@TC:1539054140>
#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: BEACONDEV3

# Tue Oct  9 11:02:20 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1539054141> | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1539054141> | Running in 64-bit mode 
@N: : <!@TM:1539054141> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1539054141> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\fpga_oled_ssd1306\src\SSD1306.v" (library work)
@I:"C:\fpga_oled_ssd1306\src\SSD1306.v":"C:\fpga_oled_ssd1306\src\SSD1306_ROM_cfg_mod_header.v" (library work)
@I::"C:\fpga_oled_ssd1306\src\SSD1306_ROM_cfg_mod.v" (library work)
@I::"C:\fpga_oled_ssd1306\src\spi_master.v" (library work)
Verilog syntax check successful!
File C:\fpga_oled_ssd1306\src\SSD1306.v changed - recompiling
Selecting top level module SSD1306
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306_ROM_cfg_mod.v:23:7:23:26:@N:CG364:@XP_MSG">SSD1306_ROM_cfg_mod.v(23)</a><!@TM:1539054141> | Synthesizing module SSD1306_ROM_cfg_mod in library work.
Opening data file SSD1306_ROM_script.mem from directory C:\fpga_oled_ssd1306\src
<font color=#A52A2A>@W:<a href="@W:CG532:@XP_HELP">CG532</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306_ROM_cfg_mod.v:31:0:31:7:@W:CG532:@XP_MSG">SSD1306_ROM_cfg_mod.v(31)</a><!@TM:1539054141> | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_oled_ssd1306\src\spi_master.v:18:7:18:17:@N:CG364:@XP_MSG">spi_master.v(18)</a><!@TM:1539054141> | Synthesizing module spi_master in library work.

	WORD_LEN=32'b00000000000000000000000000001000
	PRESCALLER_SIZE=32'b00000000000000000000000000001000
	state_idle=1'b0
	state_busy=1'b1
   Generated name = spi_master_8s_8s_0_1
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="C:\fpga_oled_ssd1306\src\spi_master.v:78:0:78:6:@W:CL113:@XP_MSG">spi_master.v(78)</a><!@TM:1539054141> | Feedback mux created for signal prescallerbuff[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.</font>
<font color=#A52A2A>@W:<a href="@W:CL113:@XP_HELP">CL113</a> : <a href="C:\fpga_oled_ssd1306\src\spi_master.v:78:0:78:6:@W:CL113:@XP_MSG">spi_master.v(78)</a><!@TM:1539054141> | Feedback mux created for signal inbufffullp. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:31:7:31:14:@N:CG364:@XP_MSG">SSD1306.v(31)</a><!@TM:1539054141> | Synthesizing module SSD1306 in library work.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[6] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[7] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[8] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[9] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[10] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[11] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[12] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[13] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@N:CL189:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Register bit repeat_count[14] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:180:0:180:6:@W:CL279:@XP_MSG">SSD1306.v(180)</a><!@TM:1539054141> | Pruning register bits 14 to 1 of repeat_count[14:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 83MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct  9 11:02:21 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1539054141> | Running in 64-bit mode 
File C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:31:7:31:14:@N:NF107:@XP_MSG">SSD1306.v(31)</a><!@TM:1539054141> | Selected library: work cell: SSD1306 view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:31:7:31:14:@N:NF107:@XP_MSG">SSD1306.v(31)</a><!@TM:1539054141> | Selected library: work cell: SSD1306 view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct  9 11:02:21 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct  9 11:02:21 2018

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1539054140>

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Database state : C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\|rev_1
<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1539054143> | Running in 64-bit mode 
File C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_comp.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:31:7:31:14:@N:NF107:@XP_MSG">SSD1306.v(31)</a><!@TM:1539054143> | Selected library: work cell: SSD1306 view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\fpga_oled_ssd1306\src\SSD1306.v:31:7:31:14:@N:NF107:@XP_MSG">SSD1306.v(31)</a><!@TM:1539054143> | Selected library: work cell: SSD1306 view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Oct  9 11:02:23 2018

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1539054140>
# Tue Oct  9 11:02:23 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport5></a>Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1539054146> | No constraint file specified. 
Linked File:  <a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306_scck.rpt:@XP_FILE">oled_ssd1306_scck.rpt</a>
Printing clock  summary report in "C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306_scck.rpt" file 
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1539054146> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1539054146> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1539054146> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1539054146> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1539054146> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1539054146> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:78:0:78:6:@N:BN362:@XP_MSG">spi_master.v(78)</a><!@TM:1539054146> | Removing sequential instance senderr (in view: work.spi_master_8s_8s_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:139:0:139:6:@N:BN362:@XP_MSG">spi_master.v(139)</a><!@TM:1539054146> | Removing sequential instance output_buffer[7:0] (in view: work.spi_master_8s_8s_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1539054146> | Incompatible asynchronous control logic preventing generated clock conversion. 
syn_allowed_resources : blockrams=10  set on top level netlist SSD1306

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start                                   Requested     Requested     Clock                                                Clock                     Clock
Level     Clock                                   Frequency     Period        Type                                                 Group                     Load 
------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       SSD1306|clk_50M                         100.0 MHz     10.000        inferred                                             Autoconstr_clkgroup_0     26   
1 .         SSD1306|clk_ssd1306_derived_clock     100.0 MHz     10.000        derived (from SSD1306|clk_50M)                       Autoconstr_clkgroup_0     102  
2 ..          SSD1306|wr_spi_derived_clock        100.0 MHz     10.000        derived (from SSD1306|clk_ssd1306_derived_clock)     Autoconstr_clkgroup_0     7    
2 ..          SSD1306|rd_spi_derived_clock        100.0 MHz     10.000        derived (from SSD1306|clk_ssd1306_derived_clock)     Autoconstr_clkgroup_0     1    
==================================================================================================================================================================



Clock Load Summary
***********************

                                      Clock     Source                        Clock Pin                Non-clock Pin     Non-clock Pin
Clock                                 Load      Pin                           Seq Example              Seq Example       Comb Example 
--------------------------------------------------------------------------------------------------------------------------------------
SSD1306|clk_50M                       26        clk_50M(port)                 clk_ssd1306_0.C          -                 -            
SSD1306|clk_ssd1306_derived_clock     102       clk_ssd1306_0.Q[0](dffre)     oled_dc.C                -                 -            
SSD1306|wr_spi_derived_clock          7         wr_spi_0.Q[0](dffr)           spi0.inbufffullp_0.C     -                 -            
SSD1306|rd_spi_derived_clock          1         rd_spi_0.Q[0](dffr)           spi0.charreceivedn.C     -                 -            
======================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:101:0:101:6:@W:MT529:@XP_MSG">ssd1306.v(101)</a><!@TM:1539054146> | Found inferred clock SSD1306|clk_50M which controls 26 sequential elements including cnt[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 110 clock pin(s) of sequential element(s)
0 instances converted, 110 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_prem.srm@|S:clk_50M@|E:cnt[0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7 @XP_NAMES_BY_PROP">ClockId_0_7</a>       clk_50M             Unconstrained_port     26         cnt[0]         
=======================================================================================
================================================================= Gated/Generated Clocks =================================================================
Clock Tree ID     Driving Element        Drive Element Type     Unconverted Fanout     Sample Instance          Explanation                               
----------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_prem.srm@|S:wr_spi_0.Q[0]@|E:spi0.input_buffer[7]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       wr_spi_0.Q[0]          dffr                   7                      spi0.input_buffer[7]     Derived clock on input (not legal for GCC)
<a href="@|L:C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_prem.srm@|S:clk_ssd1306_0.Q[0]@|E:repeat_count_0[0]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       clk_ssd1306_0.Q[0]     dffre                  102                    repeat_count_0[0]        Derived clock on input (not legal for GCC)
<a href="@|L:C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_prem.srm@|S:rd_spi_0.Q[0]@|E:spi0.charreceivedn@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       rd_spi_0.Q[0]          dffr                   1                      spi0.charreceivedn       Derived clock on input (not legal for GCC)
==========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: : <!@TM:1539054146> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1539054146> | Writing default property annotation file C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 104MB peak: 190MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Tue Oct  9 11:02:26 2018

###########################################################]

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<!@TC:1539054140>
# Tue Oct  9 11:02:26 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport8></a>Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1539054151> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1539054151> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1539054151> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:65:0:65:6:@W:BN132:@XP_MSG">spi_master.v(65)</a><!@TM:1539054151> | Removing sequential instance spi0.input_buffer[7] because it is equivalent to instance spi0.input_buffer[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>

Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1539054151> | Auto Constrain mode is enabled 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance spi0.inbufffullp. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance spi0.inbufffulln. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0000000000000000000000000" on instance cnt[24:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance repeat_count[0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0000000000000000000000000000" on instance saved_elapsed_time[27:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance clk_ssd1306. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance internal_state_machine. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0000000000000000000000000000" on instance elapsed_time[27:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance wr_spi. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance wait_spi. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1539054151> | Applying initial value "0" on instance rd_spi. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:65:0:65:6:@W:BN132:@XP_MSG">spi_master.v(65)</a><!@TM:1539054151> | Removing instance spi0.input_buffer[3] because it is equivalent to instance spi0.input_buffer[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:65:0:65:6:@W:BN132:@XP_MSG">spi_master.v(65)</a><!@TM:1539054151> | Removing instance spi0.input_buffer[2] because it is equivalent to instance spi0.input_buffer[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:65:0:65:6:@W:BN132:@XP_MSG">spi_master.v(65)</a><!@TM:1539054151> | Removing instance spi0.input_buffer[1] because it is equivalent to instance spi0.input_buffer[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:65:0:65:6:@W:BN132:@XP_MSG">spi_master.v(65)</a><!@TM:1539054151> | Removing instance spi0.input_buffer[5] because it is equivalent to instance spi0.input_buffer[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:139:0:139:6:@N:MO231:@XP_MSG">spi_master.v(139)</a><!@TM:1539054151> | Found counter in view:work.spi_master_8s_8s_0_1(verilog) instance sckint[4:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\fpga_oled_ssd1306\src\spi_master.v:139:0:139:6:@N:MO231:@XP_MSG">spi_master.v(139)</a><!@TM:1539054151> | Found counter in view:work.spi_master_8s_8s_0_1(verilog) instance prescaller_cnt[7:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306_rom_cfg_mod.v:32:14:32:24:@N:MO106:@XP_MSG">ssd1306_rom_cfg_mod.v(32)</a><!@TM:1539054151> | Found ROM oled_rom_init.dout_1[47:0] (in view: work.SSD1306(verilog)) with 128 words by 48 bits.

Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance repeat_count_0[0] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[0] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[1] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[2] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[3] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[4] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[5] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[6] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[7] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[8] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[9] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[10] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[11] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[12] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[13] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[14] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[15] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[16] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[17] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[18] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[19] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[20] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[21] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[22] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[23] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[24] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[25] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[26] (in view: work.SSD1306(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\fpga_oled_ssd1306\src\ssd1306.v:180:0:180:6:@N:BN362:@XP_MSG">ssd1306.v(180)</a><!@TM:1539054151> | Removing sequential instance saved_elapsed_time[27] (in view: work.SSD1306(verilog)) because it does not drive other instances.

Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 200MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		     2.54ns		 244 /       102

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 200MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1539054151> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 200MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 125MB peak: 200MB)

Writing Analyst data base C:\fpga_oled_ssd1306\impl\synthesize\rev_1\synwork\oled_ssd1306_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 200MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 200MB)

@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1539054151> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1539054151> | Synopsys Constraint File capacitance units using default value of 1pF  
@A:<a href="@A:BN540:@XP_HELP">BN540</a> : <!@TM:1539054151> | No min timing constraints supplied; adding min timing constraints 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 200MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 200MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1539054151> | Found inferred clock SSD1306|clk_50M with period 10.00ns. Please declare a user-defined clock on port clk_50M.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1539054151> | Found clock SSD1306|clk_ssd1306_derived_clock with period 10.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1539054151> | Found clock SSD1306|rd_spi_derived_clock with period 10.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1539054151> | Found clock SSD1306|wr_spi_derived_clock with period 10.00ns  


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
<a name=pnr10></a># Timing Report written on Tue Oct  9 11:02:30 2018</a>
#


Top view:               SSD1306
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1539054151> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1539054151> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary11></a>Performance Summary</a>
*******************


Worst slack in design: 1.459

                                      Requested     Estimated     Requested     Estimated               Clock                                                Clock                
Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type                                                 Group                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SSD1306|clk_50M                       100.0 MHz     121.2 MHz     10.000        8.253         1.747     inferred                                             Autoconstr_clkgroup_0
SSD1306|clk_ssd1306_derived_clock     100.0 MHz     108.9 MHz     10.000        9.185         1.630     derived (from SSD1306|clk_50M)                       Autoconstr_clkgroup_0
SSD1306|rd_spi_derived_clock          100.0 MHz     117.1 MHz     10.000        8.541         1.459     derived (from SSD1306|clk_ssd1306_derived_clock)     Autoconstr_clkgroup_0
SSD1306|wr_spi_derived_clock          100.0 MHz     173.6 MHz     10.000        5.761         4.239     derived (from SSD1306|clk_ssd1306_derived_clock)     Autoconstr_clkgroup_0
System                                100.0 MHz     866.6 MHz     10.000        1.154         8.846     system                                               system_clkgroup      
==================================================================================================================================================================================





<a name=clockRelationships12></a>Clock Relationships</a>
*******************

Clocks                                                                |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                           Ending                             |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------
System                             SSD1306|clk_50M                    |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                             SSD1306|clk_ssd1306_derived_clock  |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                             SSD1306|rd_spi_derived_clock       |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                             SSD1306|wr_spi_derived_clock       |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|clk_50M                    System                             |  10.000      8.246   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|clk_50M                    SSD1306|clk_50M                    |  10.000      1.747   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|clk_ssd1306_derived_clock  System                             |  10.000      6.559   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|clk_ssd1306_derived_clock  SSD1306|clk_ssd1306_derived_clock  |  10.000      1.630   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|clk_ssd1306_derived_clock  SSD1306|rd_spi_derived_clock       |  10.000      6.359   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|rd_spi_derived_clock       System                             |  10.000      8.612   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|rd_spi_derived_clock       SSD1306|clk_ssd1306_derived_clock  |  10.000      1.459   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|rd_spi_derived_clock       SSD1306|rd_spi_derived_clock       |  10.000      16.426  |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|wr_spi_derived_clock       System                             |  10.000      6.492   |  No paths    -      |  No paths    -      |  No paths    -    
SSD1306|wr_spi_derived_clock       SSD1306|clk_ssd1306_derived_clock  |  10.000      4.239   |  No paths    -      |  No paths    -      |  No paths    -    
=============================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo13></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport14></a>Detailed Report for Clock: SSD1306|clk_50M</a>
====================================



<a name=startingSlack15></a>Starting Points with Worst Slack</a>
********************************

             Starting                                         Arrival          
Instance     Reference           Type     Pin     Net         Time        Slack
             Clock                                                             
-------------------------------------------------------------------------------
cnt[12]      SSD1306|clk_50M     DFFC     Q       cnt[12]     0.367       1.747
cnt[3]       SSD1306|clk_50M     DFFC     Q       cnt[3]      0.367       1.814
cnt[11]      SSD1306|clk_50M     DFFC     Q       cnt[11]     0.367       1.814
cnt[2]       SSD1306|clk_50M     DFFC     Q       cnt[2]      0.367       1.881
cnt[13]      SSD1306|clk_50M     DFFC     Q       cnt[13]     0.367       2.024
cnt[18]      SSD1306|clk_50M     DFFC     Q       cnt[18]     0.367       2.024
cnt[4]       SSD1306|clk_50M     DFFC     Q       cnt[4]      0.367       2.091
cnt[16]      SSD1306|clk_50M     DFFC     Q       cnt[16]     0.367       2.091
cnt[14]      SSD1306|clk_50M     DFFC     Q       cnt[14]     0.367       2.220
cnt[21]      SSD1306|clk_50M     DFFC     Q       cnt[21]     0.367       2.220
===============================================================================


<a name=endingSlack16></a>Ending Points with Worst Slack</a>
******************************

             Starting                                           Required          
Instance     Reference           Type     Pin     Net           Time         Slack
             Clock                                                                
----------------------------------------------------------------------------------
cnt[6]       SSD1306|clk_50M     DFFC     D       cnt_3[6]      9.867        1.747
cnt[11]      SSD1306|clk_50M     DFFC     D       cnt_3[11]     9.867        1.747
cnt[12]      SSD1306|clk_50M     DFFC     D       cnt_3[12]     9.867        1.747
cnt[13]      SSD1306|clk_50M     DFFC     D       cnt_3[13]     9.867        1.747
cnt[14]      SSD1306|clk_50M     DFFC     D       cnt_3[14]     9.867        1.747
cnt[16]      SSD1306|clk_50M     DFFC     D       cnt_3[16]     9.867        1.747
cnt[18]      SSD1306|clk_50M     DFFC     D       cnt_3[18]     9.867        1.747
cnt[19]      SSD1306|clk_50M     DFFC     D       cnt_3[19]     9.867        1.747
cnt[20]      SSD1306|clk_50M     DFFC     D       cnt_3[20]     9.867        1.747
cnt[21]      SSD1306|clk_50M     DFFC     D       cnt_3[21]     9.867        1.747
==================================================================================



<a name=worstPaths17></a>Worst Path Information</a>
<a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srr:srsfC:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srs:fp:39487:40687:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      8.120
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 1.747

    Number of logic level(s):                4
    Starting point:                          cnt[12] / Q
    Ending point:                            cnt[6] / D
    The start point is clocked by            SSD1306|clk_50M [rising] on pin CLK
    The end   point is clocked by            SSD1306|clk_50M [rising] on pin CLK

Instance / Net               Pin      Pin               Arrival     No. of    
Name                Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------
cnt[12]             DFFC     Q        Out     0.367     0.367       -         
cnt[12]             Net      -        -       1.021     -           2         
clk_ssd13063_14     LUT4     I1       In      -         1.388       -         
clk_ssd13063_14     LUT4     F        Out     1.099     2.487       -         
clk_ssd13063_14     Net      -        -       0.766     -           1         
clk_ssd13063_22     LUT4     I1       In      -         3.253       -         
clk_ssd13063_22     LUT4     F        Out     1.099     4.352       -         
clk_ssd13063_22     Net      -        -       0.766     -           1         
clk_ssd13063        LUT4     I2       In      -         5.117       -         
clk_ssd13063        LUT4     F        Out     0.822     5.939       -         
clk_ssd13063        Net      -        -       1.082     -           13        
cnt_3[6]            LUT2     I1       In      -         7.021       -         
cnt_3[6]            LUT2     F        Out     1.099     8.120       -         
cnt_3[6]            Net      -        -       0.000     -           1         
cnt[6]              DFFC     D        In      -         8.120       -         
==============================================================================
Total path delay (propagation time + setup) of 8.253 is 4.619(56.0%) logic and 3.634(44.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport18></a>Detailed Report for Clock: SSD1306|clk_ssd1306_derived_clock</a>
====================================



<a name=startingSlack19></a>Starting Points with Worst Slack</a>
********************************

                       Starting                                                                 Arrival          
Instance               Reference                             Type     Pin     Net               Time        Slack
                       Clock                                                                                     
-----------------------------------------------------------------------------------------------------------------
step_id[3]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[3]        0.367       1.630
step_id[1]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[1]        0.367       1.697
step_id[0]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[0]        0.367       3.366
step_id[2]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[2]        0.367       3.576
step_id[4]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[4]        0.367       5.757
spi0.charreceivedp     SSD1306|clk_ssd1306_derived_clock     DFFE     Q       charreceivedp     0.367       6.359
spi0.inbufffulln_0     SSD1306|clk_ssd1306_derived_clock     DFFE     Q       inbufffulln       0.367       6.559
step_id[5]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[5]        0.367       7.622
step_id[6]             SSD1306|clk_ssd1306_derived_clock     DFFR     Q       step_id[6]        0.367       8.183
spi0.state             SSD1306|clk_ssd1306_derived_clock     DFFE     Q       state             0.367       8.551
=================================================================================================================


<a name=endingSlack20></a>Ending Points with Worst Slack</a>
******************************

                    Starting                                                                                Required          
Instance            Reference                             Type      Pin       Net                           Time         Slack
                    Clock                                                                                                     
------------------------------------------------------------------------------------------------------------------------------
step_id[6]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_s_6_0_SUM       19.867       1.630
step_id[5]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_cry_5_0_SUM     19.867       1.687
step_id[4]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_cry_4_0_SUM     19.867       1.744
step_id[3]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_cry_3_0_SUM     19.867       1.801
step_id[2]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_cry_2_0_SUM     19.867       1.858
step_id[1]          SSD1306|clk_ssd1306_derived_clock     DFFR      D         un1_step_id_1_cry_1_0_SUM     19.867       1.915
elapsed_time[0]     SSD1306|clk_ssd1306_derived_clock     DFFRE     RESET     N_96_i                        19.867       2.247
elapsed_time[1]     SSD1306|clk_ssd1306_derived_clock     DFFRE     RESET     N_96_i                        19.867       2.247
elapsed_time[2]     SSD1306|clk_ssd1306_derived_clock     DFFRE     RESET     N_96_i                        19.867       2.247
elapsed_time[3]     SSD1306|clk_ssd1306_derived_clock     DFFRE     RESET     N_96_i                        19.867       2.247
==============================================================================================================================



<a name=worstPaths21></a>Worst Path Information</a>
<a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srr:srsfC:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srs:fp:46244:59348:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.867

    - Propagation time:                      18.237
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 1.630

    Number of logic level(s):                41
    Starting point:                          step_id[3] / Q
    Ending point:                            step_id[6] / D
    The start point is clocked by            SSD1306|clk_ssd1306_derived_clock [rising] on pin CLK
    The end   point is clocked by            SSD1306|clk_ssd1306_derived_clock [rising] on pin CLK
    -Timing constraint applied as multi cycle path with factor 2 (from c:SSD1306|clk_ssd1306_derived_clock to c:SSD1306|clk_ssd1306_derived_clock)

Instance / Net                                       Pin      Pin               Arrival     No. of    
Name                                   Type          Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------
step_id[3]                             DFFR          Q        Out     0.367     0.367       -         
step_id[3]                             Net           -        -       1.082     -           16        
oled_rom_init.dout_1_47_0_.m3          LUT2          I1       In      -         1.449       -         
oled_rom_init.dout_1_47_0_.m3          LUT2          F        Out     1.099     2.548       -         
m3                                     Net           -        -       1.021     -           8         
oled_rom_init.dout_1_47_0_.m143        LUT3          I0       In      -         3.569       -         
oled_rom_init.dout_1_47_0_.m143        LUT3          F        Out     1.032     4.601       -         
m143                                   Net           -        -       0.766     -           1         
oled_rom_init.dout_1_47_0_.m147        LUT3          I0       In      -         5.367       -         
oled_rom_init.dout_1_47_0_.m147        LUT3          F        Out     1.032     6.399       -         
m147                                   Net           -        -       0.766     -           1         
oled_rom_init.dout_1_47_0_.m153_am     LUT3          I1       In      -         7.164       -         
oled_rom_init.dout_1_47_0_.m153_am     LUT3          F        Out     1.099     8.263       -         
m153_am                                Net           -        -       0.000     -           1         
oled_rom_init.dout_1_47_0_.m153        MUX2_LUT5     I0       In      -         8.263       -         
oled_rom_init.dout_1_47_0_.m153        MUX2_LUT5     O        Out     0.150     8.413       -         
encoded_step[16]                       Net           -        -       1.021     -           1         
un1_elapsed_time_cry_0_0               ALU           I0       In      -         9.434       -         
un1_elapsed_time_cry_0_0               ALU           COUT     Out     0.958     10.392      -         
un1_elapsed_time_cry_0                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_1_0               ALU           CIN      In      -         10.392      -         
un1_elapsed_time_cry_1_0               ALU           COUT     Out     0.057     10.449      -         
un1_elapsed_time_cry_1                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_2_0               ALU           CIN      In      -         10.449      -         
un1_elapsed_time_cry_2_0               ALU           COUT     Out     0.057     10.506      -         
un1_elapsed_time_cry_2                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_3_0               ALU           CIN      In      -         10.506      -         
un1_elapsed_time_cry_3_0               ALU           COUT     Out     0.057     10.563      -         
un1_elapsed_time_cry_3                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_4_0               ALU           CIN      In      -         10.563      -         
un1_elapsed_time_cry_4_0               ALU           COUT     Out     0.057     10.620      -         
un1_elapsed_time_cry_4                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_5_0               ALU           CIN      In      -         10.620      -         
un1_elapsed_time_cry_5_0               ALU           COUT     Out     0.057     10.677      -         
un1_elapsed_time_cry_5                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_6_0               ALU           CIN      In      -         10.677      -         
un1_elapsed_time_cry_6_0               ALU           COUT     Out     0.057     10.734      -         
un1_elapsed_time_cry_6                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_7_0               ALU           CIN      In      -         10.734      -         
un1_elapsed_time_cry_7_0               ALU           COUT     Out     0.057     10.791      -         
un1_elapsed_time_cry_7                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_8_0               ALU           CIN      In      -         10.791      -         
un1_elapsed_time_cry_8_0               ALU           COUT     Out     0.057     10.848      -         
un1_elapsed_time_cry_8                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_9_0               ALU           CIN      In      -         10.848      -         
un1_elapsed_time_cry_9_0               ALU           COUT     Out     0.057     10.905      -         
un1_elapsed_time_cry_9                 Net           -        -       0.000     -           1         
un1_elapsed_time_cry_10_0              ALU           CIN      In      -         10.905      -         
un1_elapsed_time_cry_10_0              ALU           COUT     Out     0.057     10.962      -         
un1_elapsed_time_cry_10                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_11_0              ALU           CIN      In      -         10.962      -         
un1_elapsed_time_cry_11_0              ALU           COUT     Out     0.057     11.019      -         
un1_elapsed_time_cry_11                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_12_0              ALU           CIN      In      -         11.019      -         
un1_elapsed_time_cry_12_0              ALU           COUT     Out     0.057     11.076      -         
un1_elapsed_time_cry_12                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_13_0              ALU           CIN      In      -         11.076      -         
un1_elapsed_time_cry_13_0              ALU           COUT     Out     0.057     11.133      -         
un1_elapsed_time_cry_13                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_14_0              ALU           CIN      In      -         11.133      -         
un1_elapsed_time_cry_14_0              ALU           COUT     Out     0.057     11.190      -         
un1_elapsed_time_cry_14                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_15_0              ALU           CIN      In      -         11.190      -         
un1_elapsed_time_cry_15_0              ALU           COUT     Out     0.057     11.247      -         
un1_elapsed_time_cry_15                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_16_0              ALU           CIN      In      -         11.247      -         
un1_elapsed_time_cry_16_0              ALU           COUT     Out     0.057     11.304      -         
un1_elapsed_time_cry_16                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_17_0              ALU           CIN      In      -         11.304      -         
un1_elapsed_time_cry_17_0              ALU           COUT     Out     0.057     11.361      -         
un1_elapsed_time_cry_17                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_18_0              ALU           CIN      In      -         11.361      -         
un1_elapsed_time_cry_18_0              ALU           COUT     Out     0.057     11.418      -         
un1_elapsed_time_cry_18                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_19_0              ALU           CIN      In      -         11.418      -         
un1_elapsed_time_cry_19_0              ALU           COUT     Out     0.057     11.475      -         
un1_elapsed_time_cry_19                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_20_0              ALU           CIN      In      -         11.475      -         
un1_elapsed_time_cry_20_0              ALU           COUT     Out     0.057     11.532      -         
un1_elapsed_time_cry_20                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_21_0              ALU           CIN      In      -         11.532      -         
un1_elapsed_time_cry_21_0              ALU           COUT     Out     0.057     11.589      -         
un1_elapsed_time_cry_21                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_22_0              ALU           CIN      In      -         11.589      -         
un1_elapsed_time_cry_22_0              ALU           COUT     Out     0.057     11.646      -         
un1_elapsed_time_cry_22                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_23_0              ALU           CIN      In      -         11.646      -         
un1_elapsed_time_cry_23_0              ALU           COUT     Out     0.057     11.703      -         
un1_elapsed_time_cry_23                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_24_0              ALU           CIN      In      -         11.703      -         
un1_elapsed_time_cry_24_0              ALU           COUT     Out     0.057     11.760      -         
un1_elapsed_time_cry_24                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_25_0              ALU           CIN      In      -         11.760      -         
un1_elapsed_time_cry_25_0              ALU           COUT     Out     0.057     11.817      -         
un1_elapsed_time_cry_25                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_26_0              ALU           CIN      In      -         11.817      -         
un1_elapsed_time_cry_26_0              ALU           COUT     Out     0.057     11.874      -         
un1_elapsed_time_cry_26                Net           -        -       0.000     -           1         
un1_elapsed_time_cry_27_0              ALU           CIN      In      -         11.874      -         
un1_elapsed_time_cry_27_0              ALU           COUT     Out     0.057     11.931      -         
un1_elapsed_time_cry_27                Net           -        -       1.549     -           4         
step_id_0_sqmuxa_2_i_o3                LUT4          I2       In      -         13.480      -         
step_id_0_sqmuxa_2_i_o3                LUT4          F        Out     0.822     14.302      -         
N_106                                  Net           -        -       1.021     -           2         
un1_step_id_1_cry_0_0                  ALU           I1       In      -         15.323      -         
un1_step_id_1_cry_0_0                  ALU           COUT     Out     1.045     16.368      -         
un1_step_id_1_cry_0                    Net           -        -       0.000     -           1         
un1_step_id_1_cry_1_0                  ALU           CIN      In      -         16.368      -         
un1_step_id_1_cry_1_0                  ALU           COUT     Out     0.057     16.425      -         
un1_step_id_1_cry_1                    Net           -        -       0.000     -           1         
un1_step_id_1_cry_2_0                  ALU           CIN      In      -         16.425      -         
un1_step_id_1_cry_2_0                  ALU           COUT     Out     0.057     16.482      -         
un1_step_id_1_cry_2                    Net           -        -       0.000     -           1         
un1_step_id_1_cry_3_0                  ALU           CIN      In      -         16.482      -         
un1_step_id_1_cry_3_0                  ALU           COUT     Out     0.057     16.539      -         
un1_step_id_1_cry_3                    Net           -        -       0.000     -           1         
un1_step_id_1_cry_4_0                  ALU           CIN      In      -         16.539      -         
un1_step_id_1_cry_4_0                  ALU           COUT     Out     0.057     16.596      -         
un1_step_id_1_cry_4                    Net           -        -       0.000     -           1         
un1_step_id_1_cry_5_0                  ALU           CIN      In      -         16.596      -         
un1_step_id_1_cry_5_0                  ALU           COUT     Out     0.057     16.653      -         
un1_step_id_1_cry_5                    Net           -        -       0.000     -           1         
un1_step_id_1_s_6_0                    ALU           CIN      In      -         16.653      -         
un1_step_id_1_s_6_0                    ALU           SUM      Out     0.563     17.216      -         
un1_step_id_1_s_6_0_SUM                Net           -        -       1.021     -           1         
step_id[6]                             DFFR          D        In      -         18.237      -         
======================================================================================================
Total path delay (propagation time + setup) of 18.370 is 10.124(55.1%) logic and 8.246(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport22></a>Detailed Report for Clock: SSD1306|rd_spi_derived_clock</a>
====================================



<a name=startingSlack23></a>Starting Points with Worst Slack</a>
********************************

                       Starting                                                            Arrival          
Instance               Reference                        Type     Pin     Net               Time        Slack
                       Clock                                                                                
------------------------------------------------------------------------------------------------------------
spi0.charreceivedn     SSD1306|rd_spi_derived_clock     DFFE     Q       charreceivedn     0.367       1.459
============================================================================================================


<a name=endingSlack24></a>Ending Points with Worst Slack</a>
******************************

                    Starting                                                                           Required          
Instance            Reference                        Type      Pin       Net                           Time         Slack
                    Clock                                                                                                
-------------------------------------------------------------------------------------------------------------------------
step_id[6]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_s_6_0_SUM       9.867        1.459
step_id[5]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_cry_5_0_SUM     9.867        1.516
step_id[4]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_cry_4_0_SUM     9.867        1.573
step_id[3]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_cry_3_0_SUM     9.867        1.630
step_id[2]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_cry_2_0_SUM     9.867        1.687
step_id[1]          SSD1306|rd_spi_derived_clock     DFFR      D         un1_step_id_1_cry_1_0_SUM     9.867        1.744
elapsed_time[0]     SSD1306|rd_spi_derived_clock     DFFRE     RESET     N_96_i                        9.867        2.076
elapsed_time[1]     SSD1306|rd_spi_derived_clock     DFFRE     RESET     N_96_i                        9.867        2.076
elapsed_time[2]     SSD1306|rd_spi_derived_clock     DFFRE     RESET     N_96_i                        9.867        2.076
elapsed_time[3]     SSD1306|rd_spi_derived_clock     DFFRE     RESET     N_96_i                        9.867        2.076
=========================================================================================================================



<a name=worstPaths25></a>Worst Path Information</a>
<a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srr:srsfC:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srs:fp:63590:66230:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      8.408
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.459

    Number of logic level(s):                9
    Starting point:                          spi0.charreceivedn / Q
    Ending point:                            step_id[6] / D
    The start point is clocked by            SSD1306|rd_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            SSD1306|clk_ssd1306_derived_clock [rising] on pin CLK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                        Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
spi0.charreceivedn          DFFE     Q        Out     0.367     0.367       -         
charreceivedn               Net      -        -       1.021     -           2         
spi0.charreceived           LUT2     I0       In      -         1.388       -         
spi0.charreceived           LUT2     F        Out     1.032     2.420       -         
charreceived                Net      -        -       1.021     -           5         
step_id_0_sqmuxa_2_i_o3     LUT4     I0       In      -         3.441       -         
step_id_0_sqmuxa_2_i_o3     LUT4     F        Out     1.032     4.473       -         
N_106                       Net      -        -       1.021     -           2         
un1_step_id_1_cry_0_0       ALU      I1       In      -         5.494       -         
un1_step_id_1_cry_0_0       ALU      COUT     Out     1.045     6.539       -         
un1_step_id_1_cry_0         Net      -        -       0.000     -           1         
un1_step_id_1_cry_1_0       ALU      CIN      In      -         6.539       -         
un1_step_id_1_cry_1_0       ALU      COUT     Out     0.057     6.596       -         
un1_step_id_1_cry_1         Net      -        -       0.000     -           1         
un1_step_id_1_cry_2_0       ALU      CIN      In      -         6.596       -         
un1_step_id_1_cry_2_0       ALU      COUT     Out     0.057     6.653       -         
un1_step_id_1_cry_2         Net      -        -       0.000     -           1         
un1_step_id_1_cry_3_0       ALU      CIN      In      -         6.653       -         
un1_step_id_1_cry_3_0       ALU      COUT     Out     0.057     6.710       -         
un1_step_id_1_cry_3         Net      -        -       0.000     -           1         
un1_step_id_1_cry_4_0       ALU      CIN      In      -         6.710       -         
un1_step_id_1_cry_4_0       ALU      COUT     Out     0.057     6.767       -         
un1_step_id_1_cry_4         Net      -        -       0.000     -           1         
un1_step_id_1_cry_5_0       ALU      CIN      In      -         6.767       -         
un1_step_id_1_cry_5_0       ALU      COUT     Out     0.057     6.824       -         
un1_step_id_1_cry_5         Net      -        -       0.000     -           1         
un1_step_id_1_s_6_0         ALU      CIN      In      -         6.824       -         
un1_step_id_1_s_6_0         ALU      SUM      Out     0.563     7.387       -         
un1_step_id_1_s_6_0_SUM     Net      -        -       1.021     -           1         
step_id[6]                  DFFR     D        In      -         8.408       -         
======================================================================================
Total path delay (propagation time + setup) of 8.541 is 4.457(52.2%) logic and 4.084(47.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport26></a>Detailed Report for Clock: SSD1306|wr_spi_derived_clock</a>
====================================



<a name=startingSlack27></a>Starting Points with Worst Slack</a>
********************************

                         Starting                                                              Arrival          
Instance                 Reference                        Type     Pin     Net                 Time        Slack
                         Clock                                                                                  
----------------------------------------------------------------------------------------------------------------
spi0.inbufffullp_0       SSD1306|wr_spi_derived_clock     DFFE     Q       inbufffullp         0.367       4.239
spi0.input_buffer[0]     SSD1306|wr_spi_derived_clock     DFFE     Q       input_buffer[0]     0.367       7.447
================================================================================================================


<a name=endingSlack28></a>Ending Points with Worst Slack</a>
******************************

                           Starting                                                      Required          
Instance                   Reference                        Type     Pin     Net         Time         Slack
                           Clock                                                                           
-----------------------------------------------------------------------------------------------------------
spi0.shift_reg_out[0]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[1]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[2]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[3]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[4]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[5]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[6]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.shift_reg_out[7]      SSD1306|wr_spi_derived_clock     DFFE     CE      N_34        9.867        4.239
spi0.prescaller_cnt[0]     SSD1306|wr_spi_derived_clock     DFFE     CE      N_283_i     9.867        4.306
spi0.prescaller_cnt[1]     SSD1306|wr_spi_derived_clock     DFFE     CE      N_283_i     9.867        4.306
===========================================================================================================



<a name=worstPaths29></a>Worst Path Information</a>
<a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srr:srsfC:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srs:fp:70397:71198:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      5.628
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 4.239

    Number of logic level(s):                2
    Starting point:                          spi0.inbufffullp_0 / Q
    Ending point:                            spi0.shift_reg_out[0] / CE
    The start point is clocked by            SSD1306|wr_spi_derived_clock [rising] on pin CLK
    The end   point is clocked by            SSD1306|clk_ssd1306_derived_clock [rising] on pin CLK

Instance / Net                        Pin      Pin               Arrival     No. of    
Name                         Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
spi0.inbufffullp_0           DFFE     Q        Out     0.367     0.367       -         
inbufffullp                  Net      -        -       1.021     -           3         
spi0._mosi_0_sqmuxa_0_a3     LUT3     I1       In      -         1.388       -         
spi0._mosi_0_sqmuxa_0_a3     LUT3     F        Out     1.099     2.487       -         
_mosi_0_sqmuxa               Net      -        -       1.021     -           5         
spi0.un1_ss7_2_i_0[0]        LUT3     I1       In      -         3.508       -         
spi0.un1_ss7_2_i_0[0]        LUT3     F        Out     1.099     4.607       -         
N_34                         Net      -        -       1.021     -           8         
spi0.shift_reg_out[0]        DFFE     CE       In      -         5.628       -         
=======================================================================================
Total path delay (propagation time + setup) of 5.761 is 2.698(46.8%) logic and 3.063(53.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport30></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack31></a>Starting Points with Worst Slack</a>
********************************

                                    Starting                                           Arrival          
Instance                            Reference     Type     Pin     Net                 Time        Slack
                                    Clock                                                               
--------------------------------------------------------------------------------------------------------
spi0.charreceivedn_i                System        INV      O       charreceivedn_i     0.000       8.846
spi0.charreceivedp_i                System        INV      O       charreceivedp_i     0.000       8.846
clk_ssd1306_i_i                     System        INV      O       clk_ssd1306_i_i     0.000       8.846
oled_rom_init.dout_1_47_0_.I_1      System        INV      O       step_id_i[3]        0.000       8.846
oled_rom_init.dout_1_47_0_.I_2      System        INV      O       step_id_i[0]        0.000       8.846
oled_rom_init.dout_1_47_0_.I_3      System        INV      O       step_id_i[1]        0.000       8.846
oled_rom_init.dout_1_47_0_.i3_i     System        INV      O       step_id_i[2]        0.000       8.846
spi0.inbufffulln_i                  System        INV      O       inbufffulln_i       0.000       8.846
spi0.inbufffullp_i                  System        INV      O       inbufffullp_i       0.000       8.846
rst_n_ibuf_RNIBNDC                  System        INV      O       N_128_0             0.000       8.846
========================================================================================================


<a name=endingSlack32></a>Ending Points with Worst Slack</a>
******************************

                         Starting                                            Required          
Instance                 Reference     Type      Pin     Net                 Time         Slack
                         Clock                                                                 
-----------------------------------------------------------------------------------------------
spi0.charreceivedn       System        DFFE      D       charreceivedn_i     9.867        8.846
spi0.charreceivedp       System        DFFE      D       charreceivedp_i     9.867        8.846
clk_ssd1306_0            System        DFFCE     D       clk_ssd1306_i_i     9.867        8.846
spi0.inbufffulln_0       System        DFFE      D       inbufffulln_i       9.867        8.846
spi0.inbufffullp_0       System        DFFE      CE      ss7_i               9.867        8.846
spi0.inbufffullp_0       System        DFFE      D       inbufffullp_i       9.867        8.846
spi0.input_buffer[0]     System        DFFE      CE      ss7_i               9.867        8.846
led[0]                   System        DFF       D       step_id_i[3]        9.867        8.846
led[1]                   System        DFF       D       step_id_i[2]        9.867        8.846
led[2]                   System        DFF       D       step_id_i[1]        9.867        8.846
===============================================================================================



<a name=worstPaths33></a>Worst Path Information</a>
<a href="C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srr:srsfC:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.srs:fp:75957:76212:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.846

    Number of logic level(s):                0
    Starting point:                          spi0.charreceivedn_i / O
    Ending point:                            spi0.charreceivedn / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            SSD1306|rd_spi_derived_clock [rising] on pin CLK

Instance / Net                    Pin      Pin               Arrival     No. of    
Name                     Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
spi0.charreceivedn_i     INV      O        Out     0.000     0.000       -         
charreceivedn_i          Net      -        -       1.021     -           1         
spi0.charreceivedn       DFFE     D        In      -         1.021       -         
===================================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 200MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 200MB)

---------------------------------------
<a name=resourceUsage34></a>Resource Usage Report for SSD1306 </a>

Mapping to part: gw1n_4lqfp144-6
Cell usage:
ALU             101 uses
DFF             8 uses
DFFC            25 uses
DFFCE           1 use
DFFE            29 uses
DFFR            7 uses
DFFRE           30 uses
DFFSE           2 uses
GSR             1 use
INV             12 uses
MUX2_LUT5       10 uses
MUX2_LUT6       3 uses
LUT2            40 uses
LUT3            27 uses
LUT4            48 uses

I/O ports: 13
I/O primitives: 13
IBUF           2 uses
OBUF           11 uses

I/O Register bits:                  0
Register bits not including I/Os:   102 of 3456 (2%)
Total load per clock:
   SSD1306|clk_50M: 26
   SSD1306|clk_ssd1306_derived_clock: 73
   SSD1306|rd_spi_derived_clock: 1
   SSD1306|wr_spi_derived_clock: 2

@S |Mapping Summary:
Total  LUTs: 115 (2%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 39MB peak: 200MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Tue Oct  9 11:02:30 2018

###########################################################]

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